1. Field
This disclosure is generally related to electronic design automation. More specifically, this disclosure is related to methods and apparatuses for testing a multi-port memory device to detect a realistic fault.
2. Related Art
Multi-port memory devices are becoming more common with the increasing popularity of multi-processor computing systems. A multi-port memory device plays an important role in synchronizing the operations performed by two or more microprocessors of the computing system. Therefore, it is important that the multi-port memory device is thoroughly tested, and determined to be fault-free, before the memory device is integrated into the multi-processor computing system.
However, testing a multi-port memory device poses unique challenges, which cannot be addressed by methods and apparatuses typically used for testing a single-port memory device. More specifically, a realistic fault can occur in the multi-port memory device, such that the realistic fault can be activated when simultaneous memory access operations are performed on two ports of the memory device. To make matters worse, the realistic fault can belong to one of many possible fault models for a given memory design, such as inter-port faults and cell-array faults.
Inter-port faults include realistic faults which are caused by an interference between simultaneous memory access operations, such as a short or a coupling between a word-line and a bit-line. Furthermore, a cell-array fault can exist as a combination of two weak coupling faults (note that a weak fault occurs when an operation over a cell may perturb the state of that cell, such that the perturbation is not sufficiently strong to modify the state of the cell). If the two weak faults have an additive effect, and they are activated by two memory access operations performed simultaneously from two ports of the memory device, the two weak faults can change the state of a common coupled cell. Furthermore, a combination of two or more weak faults may result in a strong fault when the combination of weak faults are excited simultaneously from the different ports of the memory device.
Note that it is not feasible to perform an exhaustive set of tests on a multi-port memory device, because doing so requires testing all possible interactions that can be performed between the set of ports of the memory device, which can result in an overall test time that requires several years to complete. Therefore, a test engineer is typically responsible for developing a custom test procedure which can cover an ideal set of the fault models for the memory device under test, and for developing a custom testing apparatus which can apply the test procedure onto the memory device. Unfortunately, if the testing procedure is hard-wired into the testing apparatus, the memory cannot utilize a new test procedure which has been created after the testing apparatus is fabricated with the multi-port memory device. These new test algorithms may be required to perform a fault diagnosis, a failure analysis, or to perform production tests, when the initial test set does not satisfy the target fault coverage.